Pulse Matched Filter Implementation for Reconfigurable Ultra-Wideband Receiver

Ultra wideband communication is one of the solutions for future wireless personal area networks because of its potential to achieve low data communication rate at 10-30 m distance with possible digital implementation. This paper presents the application specific integrated circuit implementation of a pulse matched filter for mostly digital receiver architecture. This architecture uses significant parallelism in order to speed up received pulse acquisition and synchronisation, resulting in increased power consumption. The paper presents the factors and analysis of parallelism dependency for different channel conditions and time delays. It also discusses one possible algorithm for intelligent adaptation of the parallelism in order to reduce power consumption and its design constraints.