A Low Power DDFS Design with Error Compensation Using A Nonlinear Digital-to-Analog Converter

This paper presents the architecture as well as the circuit implementation of a direct digital frequency synthesizer (DDFS) with error compensation. The proposed DDFS based on the straight line approximation with a 10-bit amplitude resolution. The proposed technique replaces the conventional ROM-based phase-to-amplitude conversion circuitry and the linear digital-to-analog converter with a nonlinear digital-to-analog converter (DAC). Thus, the overall power dissipation as well as hardware complexity can be significantly reduced. For a single 3.3-V supply, the maximum power dissipation is 3.37 mW at the clock rate of 385 MHz. The spurious free dynamic range (SFDR) of the synthesized sinusoid is -62.42 dBc at a 3 MHz output.