Optimization of Delta-Sigma ADC for Column-Level Data Conversion in CMOS Image Sensors

A delta-sigma analog-to-digital-converter (ADC) is designed, optimized and simulated for column-level data conversion in a CMOS image sensor. For a 0.18 mum process, the design achieves 80 dB of signal-to-noise ratio (SNR), including a 10 dB margin for kTC noise not simulated, and consumes 210 muW of power at a 50 kHz sampling rate. Low power is realized mainly by using a first-order architecture and minimizing the capacitors. For the modulator, a boosted-folded-cascode operational transconductance amplifier (OTA) is optimized to achieve a gain of 90 dB with a unity-gain bandwidth of 300 MHz. The decimator is also optimized by placing part of the circuit at the chip level. Zero distortion is possible in the decimator due to the discrete-time nature of the input signal. The proposed ADC allows a reduction in the read-out nonlinearity of a CMOS image sensor, enabling a high SNR to be realized.