Title :
Efficient architectures for modulo 2n−1 squares
Author :
Spyrou, A. ; Bakalis, D. ; Vergos, H.T.
Author_Institution :
Comput. Eng. & Inf. Dept., Univ. of Patras, Patras, Greece
Abstract :
Two novel architectures for designing modulo 2n-1 squarers are given. The first one does not perform any encoding on the input operand, while the second one uses Booth-encoding. Pre-layout estimates indicate that both architectures result in area and/or delay efficient modulo 2n-1 squarers. The non-encoded modulo squarers are more suitable for small values of n while the Booth-encoded modulo squarers are more suitable for medium and large values of n.
Keywords :
residue number systems; signal processing; Booth-encoding; modulo 2n-1 squares; nonencoded modulo squarers; Arithmetic; Circuits; Computer architecture; Concurrent computing; Delay estimation; Design engineering; Image coding; Informatics; Laboratories; Physics computing; Squaring operation; modulo 2n−1 arithmetic circuits; residue number system;
Conference_Titel :
Digital Signal Processing, 2009 16th International Conference on
Conference_Location :
Santorini-Hellas
Print_ISBN :
978-1-4244-3297-4
Electronic_ISBN :
978-1-4244-3298-1
DOI :
10.1109/ICDSP.2009.5201088
