Title :
All-digital 400∼900 MHz power amplifier consuming 0.03 mW/MHz using 0.18 μm CMOS
Author :
Bushnaq, Sanad ; Ikeda, Makoto ; Asada, Kunihiro
Author_Institution :
Electr. Eng., Univ. of Tokyo, Tokyo, Japan
Abstract :
In this paper, we present an all-digital Power Amplifier (PA) that is fully integrated on chip using 0.18 μm CMOS process. This PA consists of 8 output-connected all-digital inverters controlled by an 8-phase clock generated using a multistage Phase Interpolator (PI). Experimentally, our architecture showed power consumption less than 0.03 mW/MHz, and tuning range from 400 to 900 MHz. This architecture will be used with our wireless transceiver that applies a modified BPSK as modulation.
Keywords :
CMOS analogue integrated circuits; UHF power amplifiers; all-digital power amplifier; frequency 400 MHz to 900 MHz; modified BPSK; multistage phase interpolator; size 0.18 mum; wireless transceiver; Binary phase shift keying; CMOS integrated circuits; Clocks; Inverters; Power amplifiers; Tuning; All-digital; Power Amplifiers;
Conference_Titel :
Electronics, Circuits and Systems (ICECS), 2011 18th IEEE International Conference on
Conference_Location :
Beirut
Print_ISBN :
978-1-4577-1845-8
Electronic_ISBN :
978-1-4577-1844-1
DOI :
10.1109/ICECS.2011.6122348
