Concept and implementation of an in-situ test structure for HTGS reliability testing of PowerFETs on a wafer level basis

Technology qualification contains a great deal of different reliability tests, which are usually run either with packaged devices or on wafer level. For discrete power FET technologies, the device itself may serve as the test structure, whereas for integrated power technologies separate power FET test structures are needed. This paper focuses on vertical trench DMOS transistors, which can be found either as discrete single transistor or as a power stage in an integrated device. Fast wafer level reliability (fWLR) tests stand out from classical reliability tests as they are performed under highly accelerated stress conditions. Its main purpose is to monitor the process reliability of dielectrics, metallization and devices during mass production. Furthermore fWLR may serve as helpful tool during technology development. This paper intends to describe the idea and the realization of a test structure, which can be used to stress trench power FET devices at elevated temperatures without the necessity of an external heat source. Special focus lies on a highly accelerated version of the high temperature gate stress (HTGS), which is routinely performed during any qualification of power devices. Other tests, which can be implemented using this type of structure, include fast tests for contaminations or mobile ions. A possible layout is presented, the functionality is outlined, thermal simulations for a realized test structure are shown and first results are presented.