Title :
Error control on in-building power line communication channels
Author :
Friedman, David ; Chan, Morgan H.L. ; Donaldson, Robert W.
Author_Institution :
Dept. of Electr. Eng., British Columbia Univ., Vancover, BC, Canada
Abstract :
Forward error correction (FEC) coding is evaluated for enhancement of reliability and information throughput on power line communication channels. Rate one-half self-orthogonal convolutional codes with majority logic decoding are considered. A (2, 1, 6) code with bit interleaving to degree 7 was particularly effective, and was implemented as a VLSI microelectronic chip. Extensive bit error rate and packet error rate tests on in-building power line links showed coding gains in excess of 15 dB at 10-3 channel error rates. Tests were conducted at data rates from 1.2 to 28.8 kb/s
Keywords :
VLSI; building wiring; carrier transmission on power lines; channel capacity; convolutional codes; decoding; error correction codes; error statistics; forward error correction; interleaved codes; majority logic; telecommunication network reliability; 1.2 to 28.8 kbit/s; 15 dB; FEC; VLSI microelectronic chip; bit error rate; bit interleaving; coding gains; forward error correction coding; in-building power line links; information throughput; majority logic decoding; packet error rate; power line communication channels; reliability; self-orthogonal convolutional codes; Convolutional codes; Decoding; Error analysis; Error correction; Forward error correction; Interleaved codes; Logic; Power line communications; Testing; Throughput;
Conference_Titel :
Communications, Computers and Signal Processing, 1993., IEEE Pacific Rim Conference on
Conference_Location :
Victoria, BC
Print_ISBN :
0-7803-0971-5
DOI :
10.1109/PACRIM.1993.407193
