A novel multiprocessor cache memory

Author

Luo, Xiao ; Muzio, Jon C.

Author_Institution

Dept. of Comput. Sci., Victoria Univ., BC, Canada

Volume

1

fYear

1993

fDate

19-21 May 1993

Firstpage

145

Abstract

A reliable high-performance multiprocessor cache memory that has a reasonable hardware cost is proposed. Using VLSI technology, this cache has a single dual-port directory to deal with the interference between processor operations and data coherence operations in a multiprocessor cache for high performance at low cost. This cache has a protocol-independent structure so that any of the standard data coherence protocols can be implemented. The authors discuss the designs in the cache management unit for fault-tolerance and concurrent checking to increase the cache reliability

Keywords

VLSI; cache storage; concurrency control; distributed memory systems; fault tolerant computing; integrated circuit reliability; integrated memory circuits; memory architecture; memory protocols; VLSI technology; cache management unit; concurrent checking; data coherence protocols; fault-tolerance; hardware cost; high-performance multiprocessor cache memory; protocol-independent structure; single dual-port directory; the cache reliability; Cache memory; Coherence; Computer science; Costs; Hardware; Interference; Multiprocessing systems; Protocols; Registers; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Communications, Computers and Signal Processing, 1993., IEEE Pacific Rim Conference on

Conference_Location

Victoria, BC

Print_ISBN

0-7803-0971-5

Type

conf

DOI

10.1109/PACRIM.1993.407201

Filename

407201