A delay-optimized universal FPGA routing architecture

A universal FPGA routing architecture is presented, which ensures that every module in the FPGA including CLBs and IOBs have a uniform interconnect architecture, and the load of interconnect lines is equally distributed. So, this architecture is highly repeatable and the signal delay is predictable and regular. Furthermore, the realization of the programmable interconnect point (PIP) and the buffer driver is also optimized to benefit the signal delay up to 5%.The test results of the example chip show the reasonableness of these ideas.