DocumentCode
2925335
Title
Total-dose hardness assurance-testing for CMOS devices in space environment
Author
Kamimura, Hiroshi ; Sakagami, Masaharu ; Uchida, Shunsuke ; Kato, Masataka
Author_Institution
Hitachi Ltd., Ibaraki, Japan
fYear
1992
fDate
21-23 Jan 1992
Firstpage
202
Lastpage
209
Abstract
A practical method for total-dose hardness assurance testing for CMOS devices in a space environment is presented to predict the radiation-induced threshold voltage shift and leakage current. Simple radiation response models for the threshold voltage shift and leakage current are given. The model parameters can be determined by laboratory irradiation testing with Co-60 gamma-rays at a high dose rate. Using this method, the threshold voltage shift and leakage current of MOSFETs can be predicted at low dose rate and at any temperature from room temperature to 80°C
Keywords
CMOS integrated circuits; gamma-ray effects; insulated gate field effect transistors; integrated circuit testing; radiation hardening (electronics); semiconductor device testing; 20 to 80 degC; CMOS devices; Co-60 gamma-rays; MOSFET; laboratory irradiation testing; leakage current; radiation response models; radiation-induced threshold voltage shift; space environment; total-dose hardness assurance testing; Annealing; CMOS logic circuits; Degradation; Equations; Leakage current; MOSFETs; Semiconductor device modeling; Temperature; Testing; Threshold voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Reliability and Maintainability Symposium, 1992. Proceedings., Annual
Conference_Location
Las Vegas, NV
Print_ISBN
0-7803-0521-3
Type
conf
DOI
10.1109/ARMS.1992.187823
Filename
187823
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