DocumentCode
2925435
Title
Statistical analysis of on-chip power grid networks by variational extended truncated balanced realization method
Author
Li, Duo ; Tan, Sheldon X D ; Gengsheng Chen ; Zeng, Xuan
Author_Institution
Dept. of Electr. Eng., Univ. of California, Riverside, CA
fYear
2009
fDate
19-22 Jan. 2009
Firstpage
272
Lastpage
277
Abstract
In this paper, we present a novel statistical analysis approach for large power grid network analysis under process variations. The new algorithm is very efficient and scalable for huge networks with a large number of variational variables. This approach, called varETBR for variational extended truncated balanced realization, is based on model order reduction techniques to reduce the circuit matrices before the variational simulation. It performs the parameterized reduction on the original system using variation-bearing subspaces. varETBR calculates variational response Gramians by Monte-Carlo based numerical integration considering both system and input source variations for generating the projection subspace. varETBR is very scalable for the number of variables and is flexible for different variational distributions and ranges as demonstrated in experimental results. After the reduction, Monte-Carlo based statistical simulation is performed on the reduced system and the statistical responses of the original system are obtained thereafter. Experimental results, on a number of IBM benchmark circuits up to 1.6 million nodes, show that the varETBR can be 4500X faster than the Monte-Carlo method and is much more scalable than one of the recently proposed approaches.
Keywords
Monte Carlo methods; microprocessor chips; network analysis; power grids; statistical analysis; Monte-Carlo based numerical integration; input source variations; large power grid network analysis; model order reduction techniques; on-chip power grid networks; statistical analysis; variation-bearing subspaces; variational extended truncated balanced realization method; Analytical models; Application specific integrated circuits; Circuit simulation; Leakage current; Network-on-a-chip; Power grids; Random variables; Sampling methods; Statistical analysis; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 2009. ASP-DAC 2009. Asia and South Pacific
Conference_Location
Yokohama
Print_ISBN
978-1-4244-2748-2
Electronic_ISBN
978-1-4244-2749-9
Type
conf
DOI
10.1109/ASPDAC.2009.4796492
Filename
4796492
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