DocumentCode :
292841
Title :
A floorplanning method with topological constraint manipulation
Author :
Koide, Tetsushi ; Katsura, Yoshinori ; Yamatani, Katsumi ; Wakabayashi, Shin´ichi ; Yoshida, Noriyoshi
Author_Institution :
Fac. of Eng., Hiroshima Univ., Japan
Volume :
1
fYear :
1994
fDate :
30 May-2 Jun 1994
Firstpage :
165
Abstract :
In this paper, we propose a heuristic floorplanning method. It is based on tentative insertion of constraints, that intentionally produces redundant constraints to make it possible to search in a wide range of solution space. The proposed method reduces the total area of blocks with the removal and insertion of constraints on the critical path in both horizontal and vertical constraint graphs. Experimental results showed that the quality of solutions of the proposed method is good and even for the large number of blocks, the proposed method keeps a high quality of solution
Keywords :
circuit layout CAD; delays; graph theory; integrated circuit layout; network topology; wiring; IC layout; circuit layout design; critical path; heuristic floorplanning method; horizontal constraint graphs; placement; redundant constraints; solution space; topological constraint manipulation; total area; vertical constraint graphs; Degradation; Shape; Terminology; Tree data structures; Tree graphs; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
Type :
conf
DOI :
10.1109/ISCAS.1994.408781
Filename :
408781
Link To Document :
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