• DocumentCode
    2928546
  • Title

    A novel SPRAM (SPin-transfer torque RAM)-based reconfigurable logic block for 3D-stacked reconfigurable spin processor

  • Author

    Sekikawa, M. ; Kiyoyama, K. ; Hasegawa, H. ; Miura, K. ; Fukushima, T. ; Ikeda, S. ; Tanaka, T. ; Ohno, H. ; Koyanagi, M.

  • Author_Institution
    Dept. of Bioeng. & Robot., Tohoku Univ., Sendai
  • fYear
    2008
  • fDate
    15-17 Dec. 2008
  • Firstpage
    1
  • Lastpage
    3
  • Abstract
    A novel reconfigurable logic block with SPRAM (spin-transfer torque RAM) is demonstrated. Magnetic elements of 50 times 200 nm2 in area and CMOS logic are fully integrated. Laboratory experimental results show that our reconfigurable logic block achieves 25 MHz read out operation with the magnetic resistance of 1.62 kOmega (parallel) and the MR ratio is 91.7 %.
  • Keywords
    CMOS logic circuits; random-access storage; 3D-stacked reconfigurable spin processor; CMOS logic; frequency 25 MHz; reconfigurable logic block; spin-transfer torque RAM; CMOS logic circuits; Immune system; Integrated circuit interconnections; Laboratories; Logic devices; Magnetic field measurement; Power supplies; Random access memory; Reconfigurable logic; Torque;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 2008. IEDM 2008. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    8164-2284
  • Print_ISBN
    978-1-4244-2377-4
  • Electronic_ISBN
    8164-2284
  • Type

    conf

  • DOI
    10.1109/IEDM.2008.4796645
  • Filename
    4796645
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2928546