DocumentCode
292871
Title
Efficient and robust test generation-based timing analysis
Author
Silva, João P Marques ; Sakallah, Karem A.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
Volume
1
fYear
1994
fDate
30 May-2 Jun 1994
Firstpage
303
Abstract
This paper describes a new path sensitization model in which search-space pruning techniques commonly used in test pattern generation can be applied to timing analysis. A safe static sensitization criterion, equivalent to floating-mode sensitization, is proposed and represented in the new path sensitization model. This model has been used to implement a timing analysis tool, TA-LEAP, and preliminary results indicate significant performance gains over previous methods
Keywords
circuit analysis computing; combinational circuits; delays; logic testing; timing; TA-LEAP; floating-mode sensitization; logic circuits; path sensitization model; search-space pruning techniques; static sensitization criterion; test generation-based timing analysis; test pattern generation; timing analysis tool; Algorithm design and analysis; Artificial intelligence; Combinational circuits; Pattern analysis; Performance analysis; Performance gain; Propagation delay; Robustness; Testing; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location
London
Print_ISBN
0-7803-1915-X
Type
conf
DOI
10.1109/ISCAS.1994.408815
Filename
408815
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