An algorithm for the place-and-route problem in the layout of analog circuits

This paper presents an optimization algorithm which simultaneously deals with the problems of placement and global routing in an analog macrocell layout style. The optimization process is based on a simulated annealing algorithm. We evaluate the physical placement of the cells and estimate the global routing for each intermediate solution generated. The basic idea, that together with an appropriate heuristic make the algorithm extremely efficient, consist of maintaining the same basic representative structure (slicing structures) for both problems. This method enables us to impose symmetry conditions and to penalize the existence of sensitive and noisy nets in the same channel