Statistical investigation of the floating gate memory cell leakage through high-k interpoly dielectrics and its impact on scalability and reliability

In this work, we investigate the floating gate (FG) cell leakage through high-k interpoly dielectrics (IPDs) using a statistical approach. The impact of defects on stack scalability is addressed from a NAND technology perspective. Trap distributions are extracted from high-temperature retention tests carried out on Al₂O₃-based IPDs. Extracted material parameters are used together with a newly developed Monte-Carlo leakage/retention simulator in order to investigate the behavior of single- and multitrap leakage paths on large Flash memory arrays and predict the failure rate.