Session 15: Quantum, power, and compound semiconductors devices - III-V MOSFETs with high k dielectrics

This session highlights recent developments in III-V MOSFETs with high-k gate dielectrics. The session opens with a talk by Goel et al., describing the impact of gate dielectric stacks on InGaAs-channel MOSFETs, including dielectric scaling for several candidate dielectrics. ZrO2 was identified as a promising choice based on leakage, thermal stability, and electrostatic control. The second paper by Sun and co-workers from IBM focuses on buried-channel In0.7Ga0.3As MOSFETs with gate scaling to 80 nm. This is followed by a surface-channel result by Xuan and colleagues at Purdue on enhancement-mode In0.75Ga0.25As-channel MOSFETs with an ALD-deposited Al2O3 gate dielectric. The channel In mole fraction and its impact on performance are also described. The fourth paper in the session by Chiang et al., describes a systematic study of Fermi level pinning in In0.2Ga0.8As MOS-C structures based on stacks of GGO and Al2O3. The next paper by Varghese and coworkers employs a wide range of analytical techniques and simulation to characterize the InGaAs/Al2O3 interface. Trap density, type, and location in position and energy are extracted. They conclude that it is possible to attain large inversion currents as the majority of traps are donor-like. The last paper in the session by Chin et al., reports a promising new surface passivation technology employing a mixture of ammonia and silane for GaAs NMOSFETs with silicon oxynitride gate dielectrics. The lowest reported sub-threshold swing was achieved for this type of device.