Simulation framework for cycle-accurate RTL modeling of partial run-time reconfiguration in VHDL

Partial run-time reconfiguration has brought forward a new dimension and many new possibilities when designing systems. However, it also leads to many new challenges that need to be addressed for partial run-time reconfiguration to be successful. One of the most significant challenges is how to perform functional verification of systems using partial run-time reconfiguration. In this paper, we propose a simulation framework for functional modeling and verification of partial run-time reconfiguration at the Register Transfer Level (RTL) using VHDL. The proposed simulation framework provides cycle-accurate modeling of the reconfiguration process using the real bitstream file, and supports both island-based and slot-based reconfigurable design styles. For slot-based design styles, the simulation framework supports modules that either occupies one slot or multiple slots, as well as module relocation.