DocumentCode :
2930144
Title :
A multi-channel low-power system-on-chip for single-unit recording and narrowband wireless transmission of neural signal
Author :
Bonfanti, A. ; Ceravolo, M. ; Zambra, G. ; Gusmeroli, R. ; Spinelli, A.S. ; Lacaita, A.L. ; Angotzi, G.N. ; Baranauskas, G. ; Fadiga, L.
Author_Institution :
Dipt. di Elettron. e Inf., Politec. di Milano, Vinci, Italy
fYear :
2010
fDate :
Aug. 31 2010-Sept. 4 2010
Firstpage :
1555
Lastpage :
1560
Abstract :
This paper reports a multi-channel neural recording system-on-chip (SoC) with digital data compression and wireless telemetry. The circuit consists of a 16 amplifiers, an analog time division multiplexer, an 8-bit SAR AD converter, a digital signal processor (DSP) and a wireless narrowband 400-MHz binary FSK transmitter. Even though only 16 amplifiers are present in our current die version, the whole system is designed to work with 64 channels demonstrating the feasibility of a digital processing and narrowband wireless transmission of 64 neural recording channels. A digital data compression, based on the detection of action potentials and storage of correspondent waveforms, allows the use of a 1.25-Mbit/s binary FSK wireless transmission. This moderate bit-rate and a low frequency deviation, Manchester-coded modulation are crucial for exploiting a narrowband wireless link and an efficient embeddable antenna. The chip is realized in a 0.35-μm CMOS process with a power consumption of 105 μW per channel (269 μW per channel with an extended transmission range of 4 m) and an area of 3.1 × 2.7 mm2. The transmitted signal is captured by a digital TV tuner and demodulated by a wideband phase-locked loop (PLL), and then sent to a PC via an FPGA module. The system has been tested for electrical specifications and its functionality verified in in-vivo neural recording experiments.
Keywords :
CMOS integrated circuits; biomedical telemetry; data compression; field programmable gate arrays; frequency shift keying; medical signal detection; neurophysiology; phase locked loops; system-on-chip; time division multiplexing; DSP; FPGA; FSK transmitter; SAR AD converter; SoC; bit rate 1.25 Mbit/s; digital data compression; digital signal processor; multichannel low-power system-on-chip; neural signal; phase-locked loop; power consumption; size 0.35 mum; time division multiplexer; wireless telemetry; Clocks; Frequency shift keying; Noise; Voltage-controlled oscillators; Wireless communication; Action Potentials; Animals; Electric Power Supplies; Electroencephalography; Equipment Design; Equipment Failure Analysis; Neurons; Rats; Signal Processing, Computer-Assisted; Telemetry;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Engineering in Medicine and Biology Society (EMBC), 2010 Annual International Conference of the IEEE
Conference_Location :
Buenos Aires
ISSN :
1557-170X
Print_ISBN :
978-1-4244-4123-5
Type :
conf
DOI :
10.1109/IEMBS.2010.5626696
Filename :
5626696
Link To Document :
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