DocumentCode :
293066
Title :
A VLSI systolic array architecture for Lempel-Ziv-based data compression
Author :
Jung, Bongjin ; Burleson, Wayne
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Volume :
3
fYear :
1994
fDate :
30 May-2 Jun 1994
Firstpage :
65
Abstract :
We present a parallel algorithm, architecture, and implementation for Lempel-Ziv-based data compression. The parallel algorithm exhibits a regular structure and is well suited for parallel VLSI array implementation. Based on our parallel algorithm, a word-parallel systolic array has been developed using systematic design methodologies. Compared to a recent systolic architecture, our array structure is substantially faster, with latency of N/2+M compared to 2N+M where M is the maximum allowable length of symbols to be encoded at each encoding step and N is the length of symbols in an encoding buffer which have already been encoded. Furthermore the architecture consumes significantly less area and has a faster clock rate
Keywords :
VLSI; parallel algorithms; pipeline processing; source coding; systolic arrays; Lempel-Ziv-based data compression; VLSI systolic array architecture; clock rate; encoding buffer; encoding step; latency; maximum allowable length; parallel algorithm; regular structure; systematic design methodologies; word-parallel systolic array; Computer architecture; Concurrent computing; Data compression; Data engineering; Delay; Design methodology; Encoding; Parallel algorithms; Systolic arrays; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
Type :
conf
DOI :
10.1109/ISCAS.1994.409103
Filename :
409103
Link To Document :
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