A pipelined architecture to map ATM cells to 622 Mb/s SONET OC-12 payloads

The Synchronous Optical Network (SONET) and Synchronous Digital Hierarchy (SDH) form a high speed data transmission standard used to transport various types of payloads. Asynchronous Transport Mode (ATM) cells are an increasingly important payload type. This paper describes two pipelined implementations of these mapping functions. The first implementation maps a stream of ATM cells into a SONET OC-12 synchronous payload envelope (SPE). The second circuit maps distinct ATM cell streams into four SONET OC-3c SPE´s, which in turn can form a SONET OC-12 signal. Both of these implementations operate at 622 Mb/s. They have been implemented on a single, Xilinx XC3195 Field Programmable Gate Array (FPGA) and have an identical physical interface. This design is part of a system line card that can transmit and receive in the above mentioned modes