New CMOS differential logic circuits for true-single-phase pipelined systems

A set of new CMOS differential logic circuits are proposed for the true-single-phase clocking scheme in the pipelined systems. All the new logic circuits are insensitive to the clock slopes and free from race problem. Using the new logic circuits, the clock loading can be greatly reduced. They can be applied to high-packing-density and high-speed CMOS pipelined systems. An experimental chip has been fabricated and measured, which partly verifies the performance of the new logic circuits