Feedback-controlled enhance-pull-down BiCMOS for sub-3-V digital circuit

Author

Tseng, Yuh-Kuang ; Cheng, Kuo-Hsing ; Wu, Chung-Yu

Author_Institution

Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan

Volume

4

fYear

1994

fDate

30 May-2 Jun 1994

Firstpage

23

Abstract

This paper describes a new feedback-controlled enhanced-pull-down BiCMOS (FC-EPD-BiCMOS) logic scheme for the low-supply-voltage operation. Through the use of the feedback-controlled enhanced-pull-down structure, the driving capability is improved and bipolar transistor saturation during operation period is avoided. Based upon the proposed. Structure, both static and differential logic gates are developed. The new BiCMOS three-input NAND gate offers 35% reduction in the propagation delay time as compared to conventional BiCMOS circuits at 2.5 V supply voltage. The proposed three-input FC-EPD-BiCMOS CPL XOR/XNOR gate has 33% improvement in delay time as compared to conventional BiCMOS 3-input XOR/XNOR gates at 2.4 V supply voltage

Keywords

BiCMOS digital integrated circuits; BiCMOS logic circuits; circuit feedback; delays; logic design; logic gates; 2.4 to 3 V; XNOR gate; XOR gate; differential logic gates; driving capability; enhance-pull-down BiCMOS structure; feedback-controlled structure; low-supply-voltage operation; propagation delay time; static logic gates; sub-3-V digital circuit; three-input NAND gate; BiCMOS integrated circuits; Bipolar transistors; Costs; Degradation; Delay effects; Digital circuits; Fabrication; Logic circuits; Low voltage; Power supplies;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on

Conference_Location

London

Print_ISBN

0-7803-1915-X

Type

conf

DOI

10.1109/ISCAS.1994.409187

Filename

409187