Design of novel serial-parallel inner-product processors

A novel, high performance serial-parallel fixed-point inner-product processor is derived using the dependence graph mapping technique. The proposed scheme is AT² efficient, offers a highly regular structure, and is ideally suited for applications requiring small processor area, large word lengths, while maintaining high speed and double precision processing. Thus, the design is well suited for VLSI and FPGA implementations. A comparison in terms of speed and area between our scheme and conventional inner-product processors is presented. The proposed hardware structure simultaneously achieves a significant time and area savings