An accurate and matching-free threshold voltage extraction scheme for MOS transistors

An accurate threshold voltage extraction scheme for MOS transistors is presented. The scheme differs from alternative methods recently reported in the literature in that it does not require matched replica of the transistor under test and thus can be applied more effectively and accurately to real-time on-chip applications where threshold voltage measurements are required for many transistors with various geometries and bias conditions. The proposed scheme is accurately implemented in a matching-free way using a ratio-independent switched-capacitor subtracting amplifier and a dynamic current mirror. Nonideal effects associated with these circuits are investigated