Logic value assignment contribution to testability analysis

Due to the increased complexity of the devices produced, test generation has become one of the more important cost factors in VLSI production. Testability measures are one attempt to reduce the test cost. There are a number of techniques adopted for the evaluation of such testability measures. Most of these are based on controllability and observability concepts. The basic idea is to associate a quantitive measure with each node in the circuit under analysis. The approach proposed in this paper operates as follows: 1) Consider the relationship among objects and evaluate testability costs accordingly; 2) Use both static and dynamic measures. Only one pass through the circuit is required. This method is more deterministic than other techniques and allows hierarchical implementation (including high level primitives)