VLSI architectures for hierarchical block matching

Hierarchical block matching is an efficient motion estimation technique which provides an adaptation of the block size and the search area, to the properties of the image. In this work, we propose two novel special-purpose architectures for implementing hierarchical block matching. The first architecture is memory-efficient, but requires a large external memory bandwidth and a large number of processors. The second architecture requires significantly fewer processors, but additional on-chip memory. We describe the processor architecture, the memory organization and the scheduling details for both the architectures