Title :
Use of multiplier blocks to reduce filter complexity
Author :
Dempster, A.G. ; Macleod, M.D.
Author_Institution :
Dept. of Eng., Cambridge Univ., UK
fDate :
30 May-2 Jun 1994
Abstract :
Methods that use multiplier blocks to evaluate the coefficients of an FIR filter are shown to be far superior, in terms of the number of adders required, to the use of binary or CSD representation. Results from two new algorithms, one of which is highly likely to be optimal under certain known conditions, are discussed
Keywords :
FIR filters; digital arithmetic; digital filters; multiplying circuits; FIR filter; algorithms; coefficients evaluation; filter complexity reduction; multiplier blocks; Adders; Algorithm design and analysis; Application specific integrated circuits; Cost function; Digital filters; Finite impulse response filter; Frequency domain analysis; Microcontrollers; Microprocessors; Topology;
Conference_Titel :
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location :
London
Print_ISBN :
0-7803-1915-X
DOI :
10.1109/ISCAS.1994.409247
