DocumentCode
293180
Title
An approach for UIO generation for FSM verification and validation
Author
Schin, D. ; Shen, Y.-N. ; Lombardi, F.
Author_Institution
Dept. of Comput. Sci., Texas A&M Univ., College Station, TX, USA
Volume
4
fYear
1994
fDate
30 May-2 Jun 1994
Firstpage
303
Abstract
This paper presents a new approach for finding the Unique Input/Output (UIO) sequences of the states in of a finite state machine (FSM). The proposed approach utilizes a different data structure for organizing the search tree. This reduces the amount of time and memory space required for finding the UIO sequences of all states of a FSM. Simulation results on sample benchmark FSMs from MCNC and commercially available protocols are provided
Keywords
VLSI; binary sequences; conformance testing; data structures; finite state machines; protocols; sequential circuits; FSM verification; MCNC; UIO generation; VLSI; binary sequences; commercially available protocols; data structure; sample benchmark FSMs; search tree; sequential behaviour; unique input/output sequences; Automata; Circuit simulation; Circuit testing; Computer science; Microcontrollers; Organizing; Protocols; System testing; Tree data structures; Very large scale integration;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location
London
Print_ISBN
0-7803-1915-X
Type
conf
DOI
10.1109/ISCAS.1994.409257
Filename
409257
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