Session 31: Solid-state and nanoelectronic devices - silicon nanowire transistors

This session focuses on silicon nanowire transistors. T. Ernst from CEA-LETI will give an invited talk on a CMOS compatible nanowire platform. He will further address applications integrating nanowires as 3D memories, oscillators and biosensors. C. Dupre et al., from CEA-LETI, MINATEC, IMEP-LAHC, INPG-MINATEC and STMicroelectronics will present the fabrication and characterization of stacked silicon nanowires with independent gates. The third paper is from R. Wang et al., of Peking University and Samsung Electronics and investigates quasi-ballistic transport and self-heating effects in gate-all-around nanowire transistors. J. Chen et al., from the University of Tokyo illustrate physical mechanisms for mobility degradation as nanowire dimensions are scaled down. This is followed by a presentation of Y.J. Yeong from the same Institute reporting on the effect of uniaxial stress on Si nanowires at room temperature. The next paper by S. Yang et al., from Seoul National University and Samsung Electronics investigates random telegraph noise in Si nanowires, which is traced back to gate oxide defects. The last paper in the session by H. Zhao et al., presents a novel technique to measure bias-dependent sub-femto farad capacitance in nanowire FETs to properly extract carrier mobilities.