Distortion compensation of multi-MESFET circuits

Author

Webster, D.R. ; Haigh, D.G. ; Parker, A.E.

Author_Institution

Dept. of Electron. & Electr. Eng., Univ. Coll. London, UK

Volume

5

fYear

1994

fDate

30 May-2 Jun 1994

Firstpage

189

Abstract

We present an analysis of a 4-FET Transconductor at medium frequencies, using a more realistic GaAs MESFET model, to calculate optimum device widths to minimise 2nd order distortion. Provisional analytical results are compared with SPICE simulations using the Parker Skellern model. A multi-FET Frequency Doubler is similarly analysed to calculate optimum device widths for high fundamental rejection and optimum load for 3rd order distortion nulling. The high frequency degradation of the 4-FET Transconductor is discussed. Simulated performance of two high frequency distortion compensated Linearised Isolator designs, together with a variation of the Frequency Doubler, show good performance at high frequencies

Keywords

MESFET circuits; SPICE; compensation; electric distortion; frequency multipliers; 4-FET transconductor; GaAs; Parker Skellern model; SPICE simulation; distortion compensation; frequency doubler; high frequencies; linearised isolator; multi-MESFET circuits; Analytical models; Circuits; FETs; Frequency synthesizers; Inverters; Isolators; MESFETs; Resistors; Transconductors; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on

Conference_Location

London

Print_ISBN

0-7803-1915-X

Type

conf

DOI

10.1109/ISCAS.1994.409335

Filename

409335