• DocumentCode
    2932406
  • Title

    10 nm bulk-planar SONOS-type memory with double tunnel junction and sub-10 nm scaling utilizing source to drain direct tunnel sub-threshold

  • Author

    Ohba, Ryuji ; Mitani, Yuichiro ; Sugiyama, Naoharu ; Fujita, Shinobu

  • Author_Institution
    Adv. LSI Technol. Lab., Toshiba Corp., Yokohama
  • fYear
    2008
  • fDate
    15-17 Dec. 2008
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    10 nm gate length bulk-planar SONOS-type memory device, where 1.1 nm Si nanocrystals are lying between double tunnel oxides, retains 2.6 decades memory window for 10 years in less than 13 V w/e voltages. Moreover, 8 nm gate-length double junction SONOS device can show the same reliable characteristics by realizing S/D direct tunnel sub-threshold. This shows that further device scaling and improvement are possible utilizing S/D direct tunnel sub-threshold. Double junction SONOS is a promising candidate for sub-10 nm region.
  • Keywords
    CMOS memory circuits; semiconductor device reliability; silicon; silicon compounds; SONOS-type memory; Si; Si nanocrystals; direct tunnel; double tunnel junction; double tunnel oxides; reliability; size 1.1 nm; size 10 nm; CMOS process; Diffraction; Facsimile; Laboratories; Large scale integration; Lithography; Nanocrystals; SONOS devices; Silicon compounds; Voltage;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electron Devices Meeting, 2008. IEDM 2008. IEEE International
  • Conference_Location
    San Francisco, CA
  • ISSN
    8164-2284
  • Print_ISBN
    978-1-4244-2377-4
  • Electronic_ISBN
    8164-2284
  • Type

    conf

  • DOI
    10.1109/IEDM.2008.4796828
  • Filename
    4796828