Author :
Veloso, A. ; Demuynck, S. ; Ercken, M. ; Goethals, A.M. ; Demand, M. ; De Marneffe, J.F. ; Altamirano, E. ; De Keersgieter, A. ; Delvaux, C. ; De Backer, J. ; Brus, S. ; Hermans, J. ; Baudemprez, B. ; Van Roey, F. ; Lorusso, G.F. ; Baerts, C. ; Goossens,
Abstract :
We report on a major advancement in full-field EUV lithography technology. A single patterning approach for contact level by EUVL (NA=0.25) was used for the fabrication of electrically functional 0.186 mum2 6T-SRAMs, with W-filled contacts. Alignment to other 193 nm immersion litho levels shows very good overlay values les20 nm. Other key features of the process are: 1) use of high-k/Metal Gate FinFETs with good gate CD control: 3sigmales7 nm after double-dipole 193 nm immersion litho (NA=0.85) and 3sigmales9 nm after double-Hard Mask gate etch; and 2) use of an ultra-thin NiPt-silicide for S/D and an optimized spacers module without Si recess at dense FINs pitch. Excellent SRAM VDD scalability down to 0.6V (SNM>0.1VDD) and healthy electrical characteristics (VT, sigma(DeltaVT), I-V) for the cell transistors are obtained.
Keywords :
SRAM chips; etching; field effect memory circuits; immersion lithography; ultraviolet lithography; EUV lithography; FinFET 6T-SRAM cell; double-hard mask gate etching; immersion lithography; patterning; wavelength 193 nm; Contacts; Electric variables; Etching; Fabrication; FinFETs; High K dielectric materials; High-K gate dielectrics; Lithography; Random access memory; Scalability;
