DocumentCode
293259
Title
A 12 bit, 2 V current-mode pipelined A/D converter using a digital CMOS process
Author
Zhang, Ligang ; Sculley, Terry ; Fiez, Terri
Author_Institution
Crystal Semicond. Corp., Austin, TX, USA
Volume
5
fYear
1994
fDate
30 May-2 Jun 1994
Firstpage
369
Abstract
The design of an A/D converter for the next generation of processes requiring lower supply voltages is explored through the design and implementation of a 12 bit converter in a 1.2 μm digital CMOS process using a 2 V analog power supply. The resulting chip is 22.4 mm 2 and is presently being tested. It is expected to achieve a 1 MHz sampling rate with an analog power dissipation of 60 mW
Keywords
CMOS digital integrated circuits; analogue-digital conversion; pipeline processing; 1 MHz; 1.2 micron; 12 bit; 2 V; 60 mW; analog power dissipation; current-mode pipelined A/D converter; digital CMOS process; low voltage design; sampling rate; Analog-digital conversion; CMOS process; CMOS technology; Dynamic range; Electricity supply industry; Power supplies; Sampling methods; Signal resolution; Switches; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 1994. ISCAS '94., 1994 IEEE International Symposium on
Conference_Location
London
Print_ISBN
0-7803-1915-X
Type
conf
DOI
10.1109/ISCAS.1994.409384
Filename
409384
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