A 16-bit current sample/hold circuit using a digital CMOS process

In current-mode circuits clock feedthrough from sampling switches is a major source of error. While this error can be reduced to only an offset in switched-capacitor circuits, it produces more severe nonlinearities in switched-current designs. If the input is held constant over several cycles, clock feedthrough errors can be significantly reduced, but for a dynamic input, the ultimate solution has been to use a large sampling capacitor and small-switches. We propose a method of building a highly accurate oversampling current-mode sample/hold circuit using feedback architectures. First, second, and third-order feedback structures are proposed and simulated, with the results showing increased precision as oversampling ratio increases. A 16-bit current sample/hold circuit using a standard digital 2 μm CMOS process is presently being designed and fabricated