Design and implementation of a hardware checkpoint/restart core

Author

Mendon, Ashwin A. ; Sass, Ron ; Baker, Zachary K. ; Tripp, Justin L.

Author_Institution

Reconfigurable Comput. Syst. Lab., Univ. of North Carolina at Charlotte, Charlotte, NC, USA

fYear

2012

fDate

25-28 June 2012

Firstpage

1

Lastpage

6

Abstract

A fast hardware-based checkpoint-restart mechanism is proposed in this paper. A circuit was developed and implemented on an FPGA as a proof-of-concept. Further the size and performance of this circuit was analyzed by instrumenting the cores and taking measurements with a commercial solid state (SATA2) drive. The same tests were measured using a modern Linux server with a conventional PCIe SATA2 host bus adaptor. The results suggest that the circuit would be a tiny fraction of a modern CMOS chip (less than 2%) while providing a significant performance advantage over a software-only solution.

Keywords

CMOS logic circuits; Linux; checkpointing; field programmable gate arrays; multiprocessing systems; performance evaluation; CMOS chip; FPGA; Linux server; PCIe SATA2 host bus adaptor; SATA2; circuit performance analysis; circuit size analysis; hardware checkpoint-restart core design; hardware checkpoint-restart core implementation; manycore processors; solid state drive; Bandwidth; Checkpointing; Field programmable gate arrays; Hardware; Nonvolatile memory; Software; Solids;

fLanguage

English

Publisher

ieee

Conference_Titel

Dependable Systems and Networks Workshops (DSN-W), 2012 IEEE/IFIP 42nd International Conference on

Conference_Location

Boston, MA

Print_ISBN

978-1-4673-2264-5

Electronic_ISBN

978-1-4673-2265-2

Type

conf

DOI

10.1109/DSNW.2012.6264676

Filename

6264676