DocumentCode :
2933836
Title :
Area-efficient line-based two-dimensional discrete wavelet transform architecture without data buffer
Author :
Cao, Peng ; Wang, Chao ; Yang, Jun ; Shi, Longxing
Author_Institution :
Nat. ASIC Syst. Eng. Technol. Res. Center, Southeast Univ., China
fYear :
2009
fDate :
June 28 2009-July 3 2009
Firstpage :
1094
Lastpage :
1097
Abstract :
An area-efficient architecture for 2D DWT is proposed in this paper based on novel decomposed lifting scheme, where no data buffer is required to preserve and reorder the intermediate data between the row and column processor. Compared with the reported research, the proposed design could benefit from the reduction of internal memory size and the number of multipliers, adders and registers. The design was implemented for 2D 9/7 and 5/3 DWT in SMIC 0.18 mum CMOS logic fabrication with 15 K equivalent 2-input NAND gates under 150 MHz, which can accommodate up to 512times512 image size with 4 K bytes on-chip dual-port RAM.
Keywords :
CMOS logic circuits; discrete wavelet transforms; 2D DWT; CMOS logic fabrication; NAND gates; area-efficient line architecture; column processor; data buffer; decomposed lifting scheme; frequency 150 MHz; on-chip dual-port RAM; row processor; size 0.18 mum; Application specific integrated circuits; CMOS logic circuits; Chaos; Computer buffers; Data engineering; Discrete wavelet transforms; Image coding; Registers; Systems engineering and theory; Transform coding; JPEG2000; VLSI architecture; decomposed lifting scheme (DLS); discrete wavelet transform (DWT); line-based;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Multimedia and Expo, 2009. ICME 2009. IEEE International Conference on
Conference_Location :
New York, NY
ISSN :
1945-7871
Print_ISBN :
978-1-4244-4290-4
Electronic_ISBN :
1945-7871
Type :
conf
DOI :
10.1109/ICME.2009.5202689
Filename :
5202689
Link To Document :
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