A 4X4-block level pipeline and bandwidth optimized motion compensation hardware design for H.264/AVC decoder

A 4x4-block level pipeline motion compensation (MC) architecture for H.264/AVC decoder with high hardware utilization and low bandwidth requirement is presented in this paper. With the proposed minimum required reference data loading (MRRD) and data reuse from upper/left block (DRUL) strategies, the memory bandwidth is reduced by 70% without violating the inherent double-z-scan order of H.264/AVC bitstream. The flexible FIR filters and row/column-based interpolation are adopted to enhance the hardware utilization. Besides, to improve the bus utilization and decoding time, an on-chip memory with transpose data access and memory preloaded techniques are used for reference data reuse. The proposed MC hardware can support 1920middot1088 30 fps 4middot4-block level pipeline in H.264/AVC decoder with less than 60 MB/s memory bandwidth and a 432-byte on-chip memory when operating at 100 MHz.