PHDPLL for SONET desynchronizer

Author

Loau, Chii-Min ; Wu, Ji-Tsu

Author_Institution

Telecommun. Labs, Chung-Li, Taiwan

fYear

1991

fDate

2-5 Dec 1991

Firstpage

402

Abstract

A novel DPLL (digital phase-locked loop) has been designed and implemented. A novel phase locking technique called phase-hopping was developed. Key features of the phase-hopping DPLL (PHDPLL) are high-speed desynchronization and very narrow bandwidth (below 1 Hz). Moreover, it can be integrated with other operation circuits on a single chip by VLSI technology. Loop characteristics of the PHDPLL have been analyzed and verified by software simulation and hardware test. The optimal parameters and performance of the PHDPLL for SONET (Synchronous Optical NETwork) desynchronizer applications are presented. When the loop bandwidth of the PHDPLL is below 0.66 Hz, it is observed that the desynchronizer´s output jitter meets the 1.5 unit interval peak-to-peak jitter specification

Keywords

digital integrated circuits; optical communication equipment; phase-locked loops; synchronisation; PHDPLL; SONET desynchronizer; Synchronous Optical NETwork; VLSI technology; digital phase-locked loop; hardware test; high-speed desynchronization; jitter specification; loop bandwidth; phase-hopping DPLL; software simulation; very narrow bandwidth; Analytical models; Bandwidth; Circuit simulation; Circuit testing; Hardware; Integrated circuit technology; Jitter; Phase locked loops; SONET; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Global Telecommunications Conference, 1991. GLOBECOM '91. 'Countdown to the New Millennium. Featuring a Mini-Theme on: Personal Communications Services

Conference_Location

Phoenix, AZ

Print_ISBN

0-87942-697-7

Type

conf

DOI

10.1109/GLOCOM.1991.188418

Filename

188418