Near-threshold full adders for ultra low-power applications

Author

Hu, Jianping ; Yu, Xiaoying

Author_Institution

Fac. of Inf. Sci. & Technol., Ningbo Univ., Ningbo, China

Volume

1

fYear

2010

fDate

1-2 Aug. 2010

Firstpage

300

Lastpage

303

Abstract

Scaling supply voltage is an efficient technique to achieve low energy delay product (EDP). This paper investigates static CMOS, DCVSL, CPL and TG logic full adders in sub-threshold and super-threshold region in terms of low EDP. All circuits are simulated with HSPICE at a PTM 65nm CMOS technology by varying supply voltages from 0.2V to 1.1V with 0.1V steps. The simulation results demonstrate that lowering supply voltage is advantageous, especially in medium-voltage region (700mv-800mv) which yields the best EDP. In addition, it is shown that the optimum supply voltage of the full adders varies slightly with logic style.

Keywords

CMOS logic circuits; SPICE; adders; logic circuits; low-power electronics; CPL; DCVSL; HSPICE; TG logic full adder; energy delay product; near-threshold full adders; size 65 nm; static CMOS; supply voltage scaling; ultra low-power application; voltage 0.1 V; voltage 0.2 V to 1.1 V; CMOS integrated circuits; Rails; Full adder; Nanometer CMOS circuits; Near-threshold logic; Ultra low lower;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits,Communications and System (PACCS), 2010 Second Pacific-Asia Conference on

Conference_Location

Beijing

Print_ISBN

978-1-4244-7969-6

Type

conf

DOI

10.1109/PACCS.2010.5626910

Filename

5626910