Achieving 100% routability with 100% utilization in a complex PLD architecture

EPLDs that feature 100% routability with 100% utilization can be viewed as a collection of low density PLDs on a single chip. Since the amount of logic mapped into the Function Block is only determined by the block´s resources, not by the routing capability of the switch, the designer can lock his pins down earlier in the design cycle and be confident that the completed design will mapped to the pre-determined pinout. More importantly, with the help of SMARTswitch, Xilinx´s EPLD feature, this pinout has a higher likelihood of being maintained during design iterations than if a device with less routing and utilization capability is used