DocumentCode
2935882
Title
Using 1149.1 for multi-drop and hierarchical system testing
Author
O´Donnell, Garret
Author_Institution
Nat. Semicond. Corp., South Portland, ME
fYear
1994
fDate
27-29 Sep 1994
Firstpage
538
Lastpage
541
Abstract
The IEEE 1149.1 boundary scan test standard has been growing in usage since its approval in 1991. As applications developed primarily for board level manufacturing test grow, an awareness and need for using this test infrastructure for system level test and integration has grown. This paper examines the methods of integrating test from design to field service, explore methods for building system level test, and propose some requirements for support and development of these test methods
Keywords
IEEE standards; automatic testing; boundary scan testing; design for testability; integrated circuit testing; logic testing; printed circuit testing; IEEE 1149.1; boundary scan test standard; hierarchical system testing; multidrop testing; system level test; Automatic testing; Hierarchical systems; Manufacturing; Performance evaluation; Pins; Semiconductor device manufacture; Semiconductor device testing; System testing; USA Councils; Wires;
fLanguage
English
Publisher
ieee
Conference_Titel
WESCON/94. Idea/Microelectronics. Conference Record
Conference_Location
Anaheim , CA
ISSN
1095-791X
Print_ISBN
0-7803-9992-7
Type
conf
DOI
10.1109/WESCON.1994.403541
Filename
403541
Link To Document