A high power CSP module with optimized design and materials

A unique design of Chip Scale Packaging (CSP) aimed at satisfying high power consumption requirement is presented. Two types of framework, namely, the Substrate-On-Chip (SOC) and the Chip-On-Board (COB) are introduced to realize either central wire-bond pads or perimeter wire-bond pads configurations. Numerical simulations using the finite-element analysis (FEA) reveal exceptional thermal resistance and mechanical behavior of the design. Extensive computational studies of the effects of die-attach and substrate materials on warping deformation and stress distribution on the die are conducted to build up baselines for design and adhesive optimization. Based on the current studies, the proposed CSP design is evinced to be a model candidate to meet the growing demand of high power and high performance requirements of the next-generation electronic packages