Charge collection in silicon strip detectors with a large strip pitch

We present a study of charge collection in silicon strip detectors for which the readout pitch is equal to the thickness of the silicon wafer and is much larger than the strip width. The charge collection efficiency and signal characteristics are measured as a function of the lateral distance of the initial ionization from the strip, for various bias voltages. We find that the charge collection efficiency is significantly degraded in the region midway between strips. A simple simulation supports the hypothesis that the effect is due to interaction of drifting holes with the silicon surface. The situation could be rectified, at the expense of greater capacitance, by greatly increasing the strip width or decreasing the pitch