Title :
Extending HyperTransport™ technology to 8.0 Gb/s in 32-nm SOI-CMOS processors
Author :
Doyle, Bruce A. ; Loke, Alvin L S ; Maheshwari, Sanjeev K. ; Wang, Charles L. ; Fischette, Dennis M. ; Cooper, Jeffrey G. ; Aggarwal, Sanjeev K. ; Wee, Tin Tin ; Lackey, Chad O. ; Kedarnath, Harishkumar S. ; Oshima, Michael M. ; Talbot, Gerry R. ; Fang, E
Author_Institution :
Adv. Micro Devices, Inc., Fort Collins, CO, USA
Abstract :
We present an 8.0-Gb/s HyperTransport™ technology I/O built in a 32-nm SOI-CMOS processor for high-performance servers. Based on a 45-nm design that caps at 6.4 Gb/s, the 32-nm transceiver achieves up to 8.0 Gb/s over long-reach board channels. Key enhancements include a high-bandwidth (>;200 MHz) PLL to attenuate high-frequency jitter in the received forwarded clock and redesigned power-hungry circuits to operate at 8.0 Gb/s within the existing 45-nm package thermal limit.
Keywords :
CMOS integrated circuits; clocks; integrated circuit design; integrated circuit packaging; jitter; microprocessor chips; phase locked loops; silicon-on-insulator; transceivers; HyperTransport technology; SOI-CMOS processors; bit rate 6.4 Gbit/s; bit rate 8 Gbit/s; clock; high-bandwidth PLL; high-frequency jitter attenuation; high-performance servers; package thermal limit; power-hungry circuit redesign; size 32 nm; size 45 nm; transceiver; Bandwidth; Bit error rate; Clocks; Frequency modulation; Jitter; Phase locked loops; Program processors;
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian
Conference_Location :
Jeju
Print_ISBN :
978-1-4577-1784-0
DOI :
10.1109/ASSCC.2011.6123620
