DocumentCode :
2941082
Title :
A 2.1-GHz PLL with −80dBc/−74dBc reference spur based on aperture-phase detector and phase-to-analog converter
Author :
Cai, Deyun ; Fu, Haipeng ; Ren, Junyan ; Li, Wei ; Li, Ning ; Yu, Hao ; Yeo, Kiat Seng
Author_Institution :
State Key Lab. of ASIC & Syst., Fudan Univ., Shanghai, China
fYear :
2011
fDate :
14-16 Nov. 2011
Firstpage :
141
Lastpage :
144
Abstract :
This paper presents a 2.1-GHz PLL with low power consumption, low in-band phase noise and low reference spur. A new aperture-phase detector (APD) compares the phases between reference and VCO output in a time window, which eliminates the power and noise contributions from the divider. At the end of phase detection, a phase-to-analog converter (PAC) generates an analog voltage in proportion to the phase error and then controls the current amplitude of the following charge pump (CP) circuit. When transferred to PLL output, CP noise is not multiplied by N2 compared with a conventional PLL, which leads to the PLL with lower in-band phase noise. In the proposed CP, the charging and discharging currents have equal pulse width and equal amplitude close to zero when PLL is locked, resulting in a low reference spur and super-low power consumption of CP. The proposed PLL is implemented in TSMC 0.13μm CMOS process, which consumes 2.5 mA from a 1.2-V supply voltage and occupies a core area of 0.48 mm × 0.86 mm excluding PAD. Measurement results indicate that the PLL achieves a reference spur level of -80dBc/-74dBc, and an in-band phase noise of -103 dBc/Hz at 100 kHz offset.
Keywords :
CMOS integrated circuits; charge pump circuits; phase convertors; phase detectors; phase locked loops; phase noise; voltage-controlled oscillators; CP noise; PLL; TSMC CMOS process; VCO; aperture-phase detector; charge pump circuit; current 2.5 mA; frequency 2.1 GHz; low in-band phase noise; low power consumption; low reference spur; phase detection; phase-to-analog converter; size 0.13 mum; time window; voltage 1.2 V; Phase frequency detector; Phase locked loops; Phase noise; Semiconductor device measurement; Timing; Voltage-controlled oscillators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian
Conference_Location :
Jeju
Print_ISBN :
978-1-4577-1784-0
Type :
conf
DOI :
10.1109/ASSCC.2011.6123622
Filename :
6123622
Link To Document :
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