Title :
A 900 Mbps single-channel capacitive I/O link for wireless wafer-level testing of integrated circuits
Author :
Lee, Dae Young ; Wentzloff, David D. ; Hayes, John P.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA
Abstract :
This paper presents a 900 Mbps capacitive I/O link for wireless wafer-level testing of integrated circuits (ICs). Pulse width modulation (PWM) is adopted to embed clock information into data signals to implement single-channel communication. PWM signals are demodulated by a delay-locked loop (DLL) based bit-slicer utilizing a 1-cycle locking phase detector (PD). DC level-shifting due to DC-unbalanced symbols is mitigated with a feed-forward clock selector. An I/O prototype, fabricated in 0.13 μm CMOS achieves a bit-error-rate (BER) less than 10-13 at 900 Mbps. The total area of both the transmitter and receiver is less than the silicon area of a conventional standard I/O cell.
Keywords :
CMOS integrated circuits; clocks; delay lock loops; error statistics; feedforward; integrated circuit testing; pulse width modulation; 1-cycle locking phase detector; BER; CMOS process; DC level-shifting; DC-unbalanced symbols; PWM signals; bit rate 900 Mbit/s; bit-error-rate; bit-slicer; data signals; delay-locked loop; feed-forward clock selector; integrated circuits; pulse width modulation; receiver; single-channel capacitive I/O link; single-channel communication; transmitter; wireless wafer-level testing; Clocks; Integrated circuits; Pulse width modulation; Receivers; Testing; Transmitters; Wireless communication;
Conference_Titel :
Solid State Circuits Conference (A-SSCC), 2011 IEEE Asian
Conference_Location :
Jeju
Print_ISBN :
978-1-4577-1784-0
DOI :
10.1109/ASSCC.2011.6123625
