Comparative study of several anti-punchthrough designs for buried channel PMOSFET

As CMOS technology is scaled down, buried channel (BC) PMOS has been replaced by surface channel (SC) PMOS due to the poor short channel effect (SCE) in BC PMOS. Until now, however, BC PMOS has been widely used even in deep submicron CMOS devices because ofits advantage of simple fabrication process, no boron penetration, high driving capability due to no gate depletion, and higher mobility compared with SC PMOS. Several approaches have been proposed to suppress SCE in BC PMOS. A 0.15/spl mu/m single gate CMOS was reported using the conventional punchthrough stopper by arsenic implantation. A tilt implanted punchthrough stopper structure by using phosphorous or arsenic implantation was also proposed. However, these techniques have the disadvantage of insufficient anti-punchthrough or low current drivability. In this paper, Double Arsenic Punchthrough Stopper (DAPS) is proposed and compared with other structures. The DAPS is formed by arsenic implantation before and after the gate definition to improve both SCE and current drivability for BC PMOS.