Localized TDDB failures related to STI corner profile in advanced embedded high voltage CMOS technologies for power management units

Gate oxide integrity issues could be a challenge when integrating high voltage devices (defined by thick gate oxide) into an increasingly advanced logic process. Localized TDDB failures due to STI corner induced gate oxide thinning at the wafer edge were found to be related to the pump port in the STI etch chamber. We showed that STI top corner rounding can be optimized by creating a "passivation-dominant" etch. Mechanisms of "double-hump" STI corner formation, design-dependent STI corner profiles and wet clean optimizations to achieve TDDB requirements were discussed. The new process showed significant yield enhancement in a state-of-the-art NXP power management unit from DC/DC converter performance improvements.