DocumentCode
2946423
Title
Memory analysis of VLSI architecture for 5/3 and 1/3 motion-compensated temporal filtering [video coding applications]
Author
Huang, Chao-Tsung ; Chen, Ching-Yeh ; Chen, Yi-Hau ; Chen, Liang-Gee
Author_Institution
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Volume
5
fYear
2005
fDate
18-23 March 2005
Abstract
To the best of authors´ knowledge, this paper presents the first work on memory analysis of VLSI architectures for motion-compensated temporal filtering (MCTF). The open-loop MCTF prediction scheme has led the revolution for hybrid video coding methods that are mainly based on the close-loop MC prediction (MCP) scheme, and it also becomes the core technology of the coming video coding standard, MPEG-21 part 13-scalable video coding (SVC). In this paper, the macroblock (MB)-level and frame-level data reuse schemes are analyzed for the MCTF. The MB-level data reuse is especially for the motion estimation (ME), and the level C+ scheme is proposed, which can further reduce the memory bandwidth of the conventional level C scheme. Frame-level data reuse schemes for MCTF are proposed according to the open-loop prediction nature.
Keywords
VLSI; motion compensation; motion estimation; video coding; MPEG-21 video coding standard; VLSI architecture memory analysis; frame-level data reuse; hybrid video coding methods; level C+ scheme; macroblock-level data reuse; memory bandwidth reduction; motion estimation; motion-compensated temporal filtering; open-loop MCTF prediction scheme; scalable video coding; Automatic voltage control; Filtering; Filters; Motion analysis; Proposals; Scalability; Static VAr compensators; Very large scale integration; Video coding; Video compression;
fLanguage
English
Publisher
ieee
Conference_Titel
Acoustics, Speech, and Signal Processing, 2005. Proceedings. (ICASSP '05). IEEE International Conference on
ISSN
1520-6149
Print_ISBN
0-7803-8874-7
Type
conf
DOI
10.1109/ICASSP.2005.1416248
Filename
1416248
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